MAX1106 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1106

Single-Supply, Low-Power, Serial 8-Bit ADCs

Maxim Integrated 

Single-Supply, Low-Power,

Serial 8-Bit ADCs

VDD

DOUT

3k

DOUT

3k

GND

a) VOL to VOH

CLOAD

CLOAD

GND

b) High-Z to VOL and VOH to VOL

Figure 1. Load Circuits for Enable Time

VDD

DOUT

3k

DOUT

3k

GND

CLOAD

CLOAD

GND

a) VOH to High-Z

b) VOL to High-Z

Figure 2. Load Circuits for Disable Time

_______________Detailed Description

The MAX1106/MAX1107 analog-to-digital converters

(ADCs) use a successive-approximation conversion

technique and input track/hold (T/H) circuitry to convert

an analog signal to an 8-bit digital output. A simple ser-

ial interface provides easy interface to microprocessors

(µPs). No external hold capacitors are required. All of

the MAX1106/MAX1107 operating modes are pin con-

figurable: internal or external reference, single-ended

or pseudo-differential unipolar conversion, and power

down. Figure 3 shows the typical operating circuit.

Analog Inputs

Track/Hold

The input architecture of the ADCs is illustrated in

Figure 4’s equivalent-input circuit of and is composed

of the T/H, the input multiplexer, the input comparator,

the switched capacitor DAC, and the auto-zero rail.

The device is in acquisition mode most of the time.

During the acquisition interval, the positive input (IN+)

is tracked and is connected to the holding capacitor

(CHOLD). The acquisition interval ends with the falling

edge of CONVST. At this point the T/H switch opens

and CHOLD is connected to the negative input (IN-),

retaining charge on CHOLD as a sample of the signal at

IN+. Once conversion is complete the T/H returns

immediately to its tracking mode.

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

allowed between conversions. The acquisition time,

tACQ, is the minimum time needed for the signal to be

acquired. It is calculated by:

tACQ = 6(RS + RIN)18pF

ANALOG

INPUTS

1µF

VDD

IN+

VDD

0.1µF

1µF

MAX1106

MAX1107

IN-

GND

ON

SHDN

OFF

REFOUT CONVST

SCLK

REFIN

VDD

CPU

I/O

SCK (SK)

DOUT

MISO (SI)

GND

Figure 3. Typical Operating Circuit

GND

REFIN

CAPACITIVE DAC

IN+

CHOLD

IN-

18pF

RIN

6.5k

HOLD

TRACK

Figure 4. Equivalent Input Circuit

COMPARATOR

AUTOZERO

RAIL

10 ______________________________________________________________________________________

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