DS1100-25 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1100-25

5-Tap Economy Timing Element (Delay Line)

Dallas Semiconductor -> Maxim Integrated 

www.maxim-ic.com

FEATURES

§ All-Silicon Timing Circuit

§ Five Taps Equally Spaced

§ 5V Operation

§ Delays are Stable and Precise

§ Both Leading- and Trailing-Edge Accuracy

§ Improved Replacement for DS1000

§ Low-Power CMOS

§ TTL/CMOS-Compatible

§ Vapor-Phase, IR, and Wave Solderable

§ Custom Delays Available

§ Fast-Turn Prototypes

§ Delays Specified Over Both Commercial and

Industrial Temperature Ranges

DS1100

5-Tap Economy Timing

Element (Delay Line)

PIN ASSIGNMENT

IN

1

TAP 2

2

TAP 4

3

GND

4

8

VCC

7

TAP 1

6

TAP 3

5

TAP 5

DS1100M DIP (300mil)

DS1100Z SO (150mil)

DS1100U µSOP

PIN DESCRIPTION

TAP 1 to TAP 5 - TAP Output Number

VCC

- +5V

GND

- Ground

IN

- Input

DESCRIPTION

The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These

devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost and

superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line

and industry-standard DIP and SO packaging. The DS1100 5-tap silicon delay line reproduces the input-

logic state at the output after a fixed delay as specified by the extension of the part number after the dash.

The DS1100 is designed to reproduce both leading and trailing edges with equal precision. Each tap is

capable of driving up to ten 74LS loads.

Dallas Semiconductor can customize standard products to meet special needs.

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