74LCX16500CW 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74LCX16500CW

Low Voltage 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs

Fairchild Semiconductor 

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FBGA

(Top Thru View)

Pin Descriptions

Pin Names

Description

A1 - A18

Data Register A Inputs/3-STATE Outputs

B1 - B18

Data Register B Inputs/3-STATE Outputs

CLKAB, CLKBA Clock Pulse Inputs

LEAB, LEBA Latch Enable Inputs

OEBA, OEBA Output Enable Inputs

FBGA Pin Assignments

1

2

3

4

5

6

A

A2

A1 OEAB GND B1

B2

B

A4

A3 LEAB CLKAB B3

B4

C

A6

A5

VCC

VCC

B5

B6

D

A8

A7 GND GND B7

B8

E

A10

A9 GND GND B9

B10

F

A12 A11 GND GND B11 B12

G

A14 A13 VCC VCC B13 B14

H

A16 A15 OEBA CLKBA B15 B16

J

A17 A18 LEBA GND B18 B17

Truth Table (Note 4)

Inputs

Output

OEAB LEAB CLKAB An

Bn

L

X

X

X

Z

H

H

X

L

L

H

H

X

H

H

H

L

↓

L

L

H

L

↓

H

H

H

L

H

X

B0 (Note 5)

H

L

L

X

B0 (Note 6)

Note 4: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,

LEBA, and CLKBA.

Note 5: Output level before the indicated steady-state input conditions

were established.

Note 6: Output level before the indicated steady-state input conditions

were established, provided that CLKAB was LOW before LEAB went LOW.

Functional Description

For A-to-B data flow, the LCX16500 operates in the trans-

parent mode when LEAB is HIGH. When LEAB is LOW,

the A data is latched if CLKAB is held at a HIGH or LOW

logic level. If LEAB is LOW, the A bus data is stored in the

latch/flip-flop on the HIGH-to-LOW transition of CLKAB.

Output-enable OEAB is active-HIGH. When OEAB is

HIGH, the outputs are active. When OEAB is LOW, the out-

puts are in the high impedance state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, and CLKBA. The output enables are com-

plementary (OEAB is active HIGH and OEBA is active

LOW).

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