ADSP-21062CS-160(RevH) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21062CS-160 Datasheet PDF : 64 Pages
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Table 14. Memory Read—Bus Master
5 V and 3.3 V
Parameter
Min
Max
Unit
Timing Requirements
tDAD
tDRLD
tHDA
tHDRH
tDAAK
tDSAK
Address Selects Delay to Data Valid1, 2
RD Low to Data Valid1
Data Hold from Address, Selects3
Data Hold from RD High3
ACK Delay from Address, Selects2, 4
ACK Delay from RD Low4
Switching Characteristics
18 + DT+W
ns
12 + 5DT/8 + W
ns
0.5
ns
2.0
ns
14 + 7DT/8 + W
ns
8 + DT/2 + W
ns
tDRHA
Address Selects Hold After RD High
0+H
ns
tDARL
Address Selects to RD Low2
2 + 3DT/8
ns
tRW
RD Pulse Width
12.5 + 5DT/8 + W
ns
tRWR
RD High to WR, RD, DMAGx Low
8 + 3DT/8 + HI
ns
tSADADC Address, Selects Setup Before ADRCLK High2
0 + DT/4
ns
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1 Data delay/setup: user must meet tDAD or tDRLD or synchronous spec tSSDATI.
2 The falling edge of MSx, SW, BMS is referenced.
3 Data hold: user must meet tHDA or tHDRH or synchronous spec tHSDATI. See Example System Hold Time Calculation on Page 48 for the calculation of hold times given capacitive
and dc loads.
4 ACK is not sampled on external memory accesses that use the internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be valid by
tDAAK or tDSAK or synchronous specification tSACKC for wait state modes external, either, or both (both, if the internal wait state is zero). For the second and subsequent cycles
of a wait stated external memory access, synchronous specifications tSACKC and tHACK must be met for wait state modes external, either, or both (both, after internal wait
states have completed).
ADDRESS
MSx, SW
BMS
RD
DATA
ACK
WR, DMAG
ADRCLK
(OUT)
tDARL
tDAAK
tDAD
tDRLD
tDSAK
tRW
tSADADC
Figure 14. Memory Read—Bus Master
tDRHA
tHDA
tHDRH
tRWR
Rev. H | Page 25 of 64 | March 2013
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