TDAT021G2 데이터 시트보기 (PDF) - Agere -> LSI Corporation
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TDAT021G2 Datasheet PDF : 310 Pages
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Advisory
May 2001
TDAT042G5 Device Advisory
for Version 1 and 1A of the Device
Path Terminator (PT)
PT1. Signal Degrade (SD) and Signal Fail (SF) Bit Behavior
Receive signal degrade and receive signal fail bits in the PT state registers (addresses 0x0838, 0x088A, 0x08DC,
and 0x092E, bits [1:0]) do not function as described. Until the signal degrade (SD) and signal fail (SF) thresholds
are programmed, the SD and SF bits will toggle on a frame-by-frame basis.
Workaround
Program thresholds during system software initialization.
Corrective Action
This functionality will be retained in its current state in future versions of the device. The advance data sheet will be
corrected to reflect the actual function of the registers.
PT2. Clear-After-Write Behavior of Signal Degrade Clear Bits
Signal degrade clear (bits 15—12) of the PT one-shot control parameters register (address 0x0AA4) are described
as one-shot, clear-after-write bits. Writing these bits should automatically set and then clear the bits. This one-shot
behavior is not observed.
Workaround
The bits must be set to 1 and then explicitly set to 0 to clear these signal degrade bits.
Corrective Action
This functionality will be retained in its current state in future versions of the device. The advance data sheet will be
corrected to reflect the actual function of the registers.
Agere Systems Inc.
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