ML6510CQ-80 데이터 시트보기 (PDF) - Micro Linear Corporation

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ML6510CQ-80

Series Programmable Adaptive Clock Manager (PACMan™)

Micro Linear Corporation 

ML6510

REGISTER DEFINITIONS

REGISTER

N

R

CM

CS

SIZE

FUNCTION

7 bit

This register is used to define the ratio for the desired frequency of the primary clock.

2 bit

This register defines the frequency of the primary clocks, CLK [0-7].

1 bit

Set CM = 1 when the PECL input reference clock is from another 6510 reference clock output. Set

CM = 0 if the clock reference is TTL or PECL from an external source and minimum phase error

between input and output is desired.

1 bit

CS = 0 selects TTL input clock, CS = 1 selects PECL input clock.

TEST

M

DDSK

1 bit

When set to 1, the PLL is bypassed for low frequency testing.

6 bit

This register is used to define the ratio for the desired frequency of the primary clock.

1 bit

When DDSK is set to 1, deskew is disabled. The chip will provide low skew clocks at the chip output

pins, but trace length variations will not be compensated. When DDSK is set to 0, normal deskew will

provide low skew clocks at the loads. This bit is only for ML6510-130.

ML6510-80 SHIFT REGISTER CHAIN

N0 N1 N2 N3 N4 N5 N6 R0 R1 CM CS TEST M0 M1 M2 M3 M4 M5

SERIAL DATA IN

(from EEPROM,

or µProcessor,

LSB

or internal ROM)

MSB LSB MSB

LSB

MSB

ML6510-130 SHIFT REGISTER CHAIN

SERIAL DATA IN

(from EEPROM,

or µProcessor,

or internal ROM)

N0 N1 N2 N3 N4 N5 N6 R0 R1 DDSK CM CS TEST M0 M1 M2 M3 M4 M5

LSB

MSB LSB MSB

LSB

MSB

14

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