EDS1232AABB 데이터 시트보기 (PDF) - Elpida Memory, Inc

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EDS1232AABB

128M bits SDRAM

Elpida Memory, Inc 

EDS1232AABB, EDS1232AATA

Read command (/CS, /CAS = Low, /RAS, /WE = High)

Read data is available after /CAS latency requirements have been met. This command sets the burst start address

given by the column address.

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0, BA1

(Bank select)

A10

Add

Col.

Column Address and and Read Command

CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)

This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally.

Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle

(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or

activate command), the Synchronous DRAM cannot accept any other command

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0, BA1

(Bank select)

A10

Add

CBR (auto) Refresh Command

Preliminary Data Sheet E0205E50 (Ver. 5.0)

14

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