M66222SP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M66222SP

128 × 8-BIT × 2 MAIL-BOX

MITSUBISHI ELECTRIC  

MITSUBISHI 〈DIGITAL ASSP〉

M66222SP/FP

128 × 8-BIT × 2 MAIL-BOX

FUNCTION

The M66222 is a mail box most suitable for inter-MCU data

communication interface. Provision of two pairs of addresses and

data buses in its shared memory cell of 128 × 8-bit configuration

allows independent and asynchronous read/write operations from/to

two access ports of A and B individually.

Two memory areas of 128 × 8-bit configuration are incorporated in

the chip. Memory area (1) is used only to perform a write operation

from A port and a read operation from B port, and memory area (2)

only to perform a read operation from A port and a write operation

from B port.

In this case, address A7A should be set to “L” when writing data from

A port in memory area (1), and address A7B should be set to “L”

when reading data from B port in memory area (1). Also, address

A7B should be set to “H” when writing data from B port in memory

area (2), and address A7A should be set to “H” when reading data

from A port in memory area (2).

Therefore, an attempt to set addresses A7A and A7B from each port

in a mode other than the above setting invalidates any read/write

operation from the corresponding port (See Table 1 and Fig 1).

As a basic write operation to memory, one of addresses A0 to A7 is

specified. The CS signal is set to “L” to place one of I/O pins in the

input mode. Also, the WE signal is set to “L”. Data at the I/O pin is

written into memory.

As a read operation, the WE signal is set to “H”. Both CS signal and

OE signal are set to “L” to place one of I/O pins in the output mode.

One of addresses A0 to A7 is specified. Data at the specified address

is thus output to the I/O pin.

When the CS signal is set to “H”, the chip enters a non-select state

which inhibits a read and write operation. At this time, the output is

placed in the floating state (high impedance state), thus allowing OR

tie with another chip. When the OE signal is set to “H”, the output

enters the floating state. In the I/O bus mode, setting the OE signal

to "H" at a write time avoids contention of I/O bus data. When the CS

signal is set to Vcc, the output enters the full stand-by state to minimize

supply current (See Tables 2 and 3).

Table 1 Port Operations and Address A7 Setting Conditions

Access

Operation port

A port

B port

Write

A7A = “L”

A7B = “H”

Read

A7A = “H”

A7B = “L”

Note 1: No input data is written into any port having address A7 set under

any condition other than Table 1. Undefined data is read to an

output pin during a read operation.

Write A7A = “L”

A port

Read A7A = “H”

Fig 1 Access from Ports

Memory area (1)

of 128-word × 8-bit

configuration

0-127 addresses

Memory area (2)

of 128-word × 8-bit

configuration

128-255 addresses

A7B = “L” Read

B port

A7B = “H” Write

Table 2 A Port Function Table

CSA WEA OEA A7A Mode

L

LL×

H

Write

Invalid

L

LHL

H

Invalid

Read

LHH ×

—

H × × × Non-select

Note 2: × indicates “L” or “H”. (Irrelevant)

“H” = High level, “L” = Low level

I/O pin

DIN

DIN

DOUT

DOUT

High impedance

High impedance

ICC

Operation

Operation

Operation

Operation

Operation

Stand-by

Table 3 B Port Function Table

CSB WEB OEB A7B

L

LL×

H

L

LHL

H

L HH ×

H× × ×

Mode

Invalid

Write

Read

Invalid

—

Non-select

I/O pin

DIN

DIN

DOUT

DOUT

High impedance

High impedance

ICC

Operation

Operation

Operation

Operation

Operation

Stand-by

2

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