
MC54/74HC175
SWITCHING WAVEFORMS
tw
tf
tr
VCC
CLOCK
90%
50%
VCC
RESET
50%
GND
10%
GND
tPHL
tw
1/fmax
Q
50%
Q or Q
90%
50%
10%
tPLH
tTLH
tPHL
tTHL
tPLH
Q
50%
trec
Figure 1.
CLOCK
VCC
50%
GND
Figure 2.
VALID
VCC
DATA
GND
tsu
th
CLOCK
VCC
50%
GND
Figure 3.
TEST CIRCUIT
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 4.
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6