ADV7194 데이터 시트보기 (PDF) - Analog Devices

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ADV7194

Professional Extended-10 Video Encoder with 54 MHz Oversampling

Analog Devices 

ADV7194

DETAILED DESCRIPTION OF FEATURES

Clocking

Single 27 MHz Clock Required to Run the Device

4؋ Oversampling with Internal 54 MHz PLL

Square Pixel Operation

Advanced Power Management

Programmable Video Control Features

Digital Noise Reduction

Black Burst Signal Generation

Pedestal Level

Hue, Brightness, Contrast and Saturation

Clamping Output signal

VBI (Vertical Blanking Interval)

Subcarrier Frequency and Phase

LUMA Delay

CHROMA Delay

Gamma Correction

Luma and Chroma Filters

Luma SSAF (Super Subalias Filter)

Average Brightness Detection

Field Counter

Interlaced/Noninterlaced Operation

Complete On-Chip Video Timing Generator

Programmable Multimode Master/Slave Operation

CGMS (Copy Generation Management System)

WSS (Wide Screen Signaling)

Closed Captioning Support

Teletext Insertion Port (PAL-WST)

2-Wire Serial MPU Interface

(I2C Compatible and Fast I2C)

I2C Registers Synchronized to VSYNC

GENERAL DESCRIPTION

The ADV7194 is an integrated Digital Video Encoder that con-

verts digital CCIR-601/656 4:2:2 10-bit (or 20-bit or 8-/16-bit)

component video data into a standard analog baseband television

signal compatible with worldwide standards. Additionally there

is the possibility to input video data in 3× 10-bit YCrCb progres-

sive scan format to facilitate interfacing devices such as progressive

scan systems.

There are six DACs available on the ADV7194, each of which

is capable of providing 4.33 mA of current. In addition to the

composite output signal there is the facility to output S-Video

(Y/C Video), RGB Video, and YUV Video. All YUV formats

(SMPTE/EBU N10, MII, or Betacam) are supported.

The on-board SSAF (Super Subalias Filter) with extended

luminance frequency response and sharp stopband attenuation

enables studio quality video playback on modern TVs, giving

optimal horizontal line resolution. An additional sharpness

control feature allows high-frequency enhancement on the lumi-

nance signal.

Y DATA

INPUT

DNR MODE

DNR CONTROL

GAIN

BLOCK SIZE CONTROL CORING GAIN DATA

BORDER AREA

CORING GAIN BORDER

BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

SUBTRACT SIGNAL IN THRESHOLD

RANGE FROM ORIGINAL SIGNAL

FILTER OUTPUT

<THRESHOLD?

FILTER OUTPUT>

THRESHOLD

DNR OUT

DNR SHARPNESS MODE

Y DATA

INPUT

DNR CONTROL

GAIN

BLOCK SIZE CONTROL CORING GAIN DATA

BORDER AREA

CORING GAIN BORDER

BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

ADD SIGNAL ABOVE THRESHOLD

RANGE TO ORIGINAL SIGNAL

FILTER OUTPUT

>THRESHOLD?

MAIN SIGNAL PATH

FILTER OUTPUT<

THRESHOLD

DNR OUT

Figure 6. Block Diagram for DNR Mode and DNR Sharp-

ness Mode

PAL_NTSC VSO/CLAMP CSO_HSO

SCL SDA ALSB

Cr0–Cr9 Cb0–Cb9 Y0–Y9

HSYNC

VSYNC

BLANK

RESET

VIDEO TIMING

GENERATOR

CGMS/WSS

AND

CLOSED CAPTIONING

CONTROL

I2C MPU PORT

M

U

YUV-TO-RGB

L

MATRIX

T

AND

I

TTX

TTXREQ

TELETEXT

INSERTION

BLOCK

10

YCrCb- Y

DNR

10

Y

BRIGHTNESS

CONTROL

AND

ADD SYNC

AND

INTERPOLATOR

PROGRAMMABLE

LUMA FILTER

AND

SHARPNESS

FILTER

YUV LEVEL

P

CONTROL

L

BLOCK

E

X

E

R

TO- 10

YUV U

MATRIX 10

V

10 10 10

AND

10

GAMMA U

CORRECTION 10

V

SATURATION

CONTROL

AND

ADD BURST

AND

PROGRAMMABLE

CHROMA

FILTER

MODULATOR

AND

HUE CONTROL

INTERPOLATOR

P0

DEMUX

P15

CLKIN

CLKOUT

REAL-TIME

SIN/COS

PLL

ADV7194

CONTROL

CIRCUIT

DDS

BLOCK

I

N

T

E

R

P

O

L

A

T

IO

NR

T

E

R

P

O

L

A

T

O

R

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

DAC

CONTROL

BLOCK

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

DAC

CONTROL

BLOCK

DAC A

DAC B

DAC C

VREF

RSET2

COMP2

DAC D

DAC F

DAC E

RSET1

COMP1

SCRESET/RTC/TR

Figure 5. Detailed Functional Block Diagram

REV. A

–11–

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