ADV7194 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
ADV7194 Datasheet PDF : 69 Pages
| |||
ADV7194
PIN FUNCTION DESCRIPTIONS
Pin
Input/
No.
Mnemonic
Output Function
1–10
P0–P9
I
11–20
Y0/P10–Y9/P19
I
21, 34, 68, 79 VDD
P
22, 33, 43, 69, DGND
G
80
23
HSYNC
I/O
24
VSYNC
I/O
25
BLANK
I/O
26–31, 75–78 Cb0–Cb9
I
32
TTXREQ
O
35, 49, 52
AGND
G
36
CLKIN
I
37
38, 48, 53
39
40
41
CLKOUT
O
VAA
P
SCL
I
SDA
I/O
SCRESET/RTC/TR I
42
ALSB
I
44
RSET2
I
45
COMP 2
O
46
DAC F
O
47
DAC E
O
50
DAC D
O
51
DAC C
O
54
DAC B
O
55
DAC A
O
56
COMP 1
O
57
VREF
I/O
58
RSET1
I
59
PAL_NTSC
I
60
RESET
I
61
CSO_HSO
O
62
VSO/TTX/CLAMP I/O
63–67, 70–74 Cr0–Cr9
I
10-Bit or 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up
on Pin P0 (Pin Number 1) in 10-bit input mode.
20-Bit or 16-Bit Multiplexed YCrCb Pixel Port or 1× 10-bit progressive scan input for Y data.
Digital Power Supply (3.3 V to 5 V).
Digital Ground.
HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output
(Master Mode) or an input (Slave Mode) and accept Sync Signals.
VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an input
(Slave Mode) and accept VSYNC as a Control Signal.
Video Blanking Control Signal. This signal is optional. For further information see Verti-
cal Blanking and Data Insertion Blanking Input section.
1 × 10-Bit Progressive Scan Input Port for Cb Data.
Teletext Data Request Output Signal, used to control teletext data transfer.
Analog Ground.
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alterna-
tively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
Clock Output Pin.
Analog Power Supply (3.3 V to 5 V).
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
Multifunctional Input: Real-Time Control (RTC) input, Timing Reset input, Subcarrier
Reset input.
TTL Address Input. This signal sets up the LSB of the MPU address.
A 1200 Ω resistor connected from this pin to AGND is used to control full-scale amplitudes
of the Video Signals from the DAC D, E, F.
Compensation Pin for DACs D, E, and F. Connect a 0.1 µF Capacitor from COMP 2 to
VAA.
S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
Composite/Y/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.
S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
Composite/Y/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.
Compensation Pin for DACs A, B, and C. Connect a 0.1 µF Capacitor from COMP 1 to
VAA.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external
VREF can not be used in 4× oversampling mode.
A 1200 Ω resistor connected from this pin to AGND is used to control full-scale amplitudes
of the Video Signals from the DAC A, B, C.
Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL.
The input resets the on-chip timing generator and sets the ADV7194 into default mode
See Appendix 8 for Default Register settings.
Dual function CSO or HSO output Sync Signal at TTL level.
Multifunctional Pin. VSO Output Sync Signal at TTL level. Teletext Data Input pin.
CLAMP TTL Output Signals can be used to drive external circuitry to enable clamping
of all Video Signals.
1 × 10-Bit Progressive Scan Input Port for Cr Data.
–10–
REV. A
Share Link: 