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74HCT9046A

PLL with bandgap controlled VCO

Philips Electronics 

Philips Semiconductors

PLL with bandgap controlled VCO

Product specification

74HCT9046A

The pump current IP is independent

from the supply voltage and is set by

the internal bandgap reference of

2.5 V.

IP = 17 × 2-R---.--5b- (A)

Rb is the external bias resistor

between pin 15 and ground.

The current and voltage transfer

function of PC2 are shown in Fig.9.

The phase comparator gain is:

Kp = -2-I--P-π-- (A ⁄ r)

Typical waveforms for the PC2 loop

locked at fc are shown in Fig.10.

When the frequencies of SIGIN and

COMPIN are equal but the phase of

SIGIN leads that of COMPIN, the up

output driver at PC2OUT is held ‘ON’

for a time corresponding to the phase

difference (ΦPCIN). When the phase of

SIGIN lags that of COMPIN, the down

or sink driver is held ‘ON’.

When the frequency of SIGIN is higher

than that of COMPIN, the source

output driver is held ‘ON’ for most of

the input signal cycle time and for the

remainder of the cycle time both

drivers are ‘OFF’ (3-state). If the

SIGIN frequency is lower than the

COMPIN frequency, then it is the sink

driver that is held ‘ON’ for most of the

cycle. Subsequently the voltage at the

capacitor (C2) of the low-pass filter

connected to PC2OUT varies until the

signal and comparator inputs are

equal in both phase and frequency. At

this stable point the voltage on C2

remains constant as the PC2 output is

in 3-state and the VCO input at pin 9

is a high impedance. Also in this

condition the signal at the phase

comparator pulse output (PCPOUT)

has a minimum output pulse width

equal to the overlap time, so can be

used for indicating a locked condition.

Thus for PC2 no phase difference

exists between SIGIN and COMPIN

over the full frequency range of the

VCO. Moreover, the power

dissipation due to the low-pass filter is

reduced because both output drivers

are OFF for most of the signal input

cycle. It should be noted that the PLL

lock range for this type of phase

comparator is equal to the capture

range and is independent of the

low-pass filter. With no signal present

at SIGIN the VCO adjust, via PC2, to

its lowest frequency.

By using current sources as charge

pump output on PC2, the dead zone

or backlash time could be reduced to

zero. Also, the pulse widening due to

the parasitic output capacitance plays

no role here. This enables a linear

transfer function, even in the vicinity

of the zero crossing. The differences

between a voltage switch charge

pump and a current switch charge

pump are shown in Fig.11.

The design of the low-pass filter is

somewhat different when using

current sources. The external resistor

R3 is no longer present when using

PC2 as phase comparator. The

current source is set by Rb. A simple

capacitor behaves as an ideal

integrator now, because the capacitor

is charged by a constant current. The

transfer function of the voltage switch

charge pump may be used. In fact it is

even more valid, because the transfer

function is no longer restricted for

small changes only. Further the

current is independent from both the

supply voltage and the voltage across

the filter. For one that is familiar with

the low-pass filter design of the

4046A a relation may show how Rb

relates with a fictive series resistance,

called R3'.

This relation can be derived by

assuming first that a voltage

controlled switch PC2 of the 4046A is

connected to the filter capacitance C2

via this fictive R3' (see Fig.8b). Then

during the PC2 output pulse the

charge current equals:

IP = V-----C---C-----–-R----V3----'C---2----(--0---)

With the initial voltage VC2(0) at:

1⁄2VCC = 2.5 V, IP = R-2---.-3-5--'

As shown before the charge current

of the current switch of the 9046A is:

IP = 17 × 2-R---.--5b-

Hence:

R3' = -R1---7-b- (Ω)

Using this equivalent resistance R3'

for the filter design the voltage can

now be expressed as a transfer

function of PC2; assuming ripple

(fr = fi) is suppressed, as:

KPC2 = 4--5--π-- (V ⁄ r)

Again this illustrates the supply

voltage independent behaviour of

PC2.

Examples of PC2 combined with a

passive filter are shown in Figs 12

and 13. Figure 12 shows that PC2

with only a C2 filter behaves as a

high-gain filter. For stability the

damped version of Fig.13 with series

resistance R4 is preferred.

Practical design values for Rb are

between 25 and 250 kΩ with

R3' = 1.5 to 15 kΩ for the filter design.

Higher values for R3' require lower

values for the filter capacitance which

is very advantageous at low values

the loop natural frequency ωn.

1999 Jan 11

9

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