Philips Semiconductors
PLL with bandgap controlled VCO
Product specification
74HCT9046A
SIG IN
COMP IN
VCO OUT
UP
DOWN
OPC IN
CURRENT AT
PC2 OUT
PC2 OUT /VCO IN
high impedance OFF state,
(zero current)
PCPOUT
The pulse overlap of the up and down signals (typically 15 ns).
Fig.10 Timing diagram for PC2.
MBD047 - 1
2.75
VCO IN
2.50
(1)
(1)
(2)
2.75
VCO IN
2.50
2.25
25
0
25
phase error (ns)
a.
2.25
25
0
25
phase error (ns)
MBD043
b.
a. Response with traditional voltage-switch charge-pump PC2OUT (4046A).
(1) Due to parasitic capacitance on PC2OUT.
(2) Backlash time (dead zone).
b. Response with current switch charge-pump PC2OUT as applied in the HCT9046A.
Fig.11 The response of a locked-loop in the vicinity of the zero crossing of the phase error.
1999 Jan 11
11