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FW801

One-Cable Transceiver/Arbiter Device

Agere -> LSI Corporation 

Data Sheet, Rev. 1

June 2001

FW801 PHY IEEE 1394A

One-Cable Transceiver/Arbiter Device

Signal Information (continued)

Table 1. Signal Descriptions (continued)

Pin

Signal*

Type

Name/Description

1

CTL0

I/O Control I/O. The CTLn signals are bidirectional communications control

signals between the PHY and the LLC. These signals control the passage

2

CTL1

of information between the two devices. Bus-keeper circuitry is built into

these terminals.

3, 4, 6, 7,

8, 9, 10,

11

D[0:7]

I/O Data I/O. The Dn signals are bidirectional and pass data between the

PHY and the LLC. Bus-keeper circuitry is built into these terminals.

19

/ISO

I

Link Interface Isolation Disable Input (Active-Low). /ISO controls the

operation of an internal pulse differentiating function used on the

PHY-LLC interface signals, CTLn and Dn, when they operate as outputs.

When /ISO is asserted low, the isolation barrier is implemented between

PHY and its LLC (as described in Annex J of IEEE 1394-1995).

/ISO is normally tied high to disable isolation differentiation. Bus-keepers

are enabled when /ISO is high (inactive) on CTL, D, and LREQ. When

/ISO is low (active), the bus-keepers are disabled. Please refer to Agere’s

application note AP98-074CMPR for more information on isolation.

14

LPS

48

LREQ

18

PD

I

Link Power Status. LPS is connected to either the VDD supplying the

LLC or to a pulsed output that is active when the LLC is powered for the

purpose of monitoring the LLC power status. If LPS is inactive for more

than 1.2 µs and less than 25 µs, interface is reset. If LPS is inactive for

greater than 25 µs, the PHY will disable to save power. FW801 continues

its repeater function.

I

Link Request. LREQ is an output from the LLC that requests the PHY to

perform some service. Bus-keeper circuitry is built into this terminal.

I

Powerdown. When asserted high, PD turns off all internal circuitry except

the bias-detect circuits that drive the CNA signal.

41

PLLVDD

—

Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry

portion of the device.

42

PLLVSS

—

Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground

plane.

37

R0

38

R1

I

Current Setting Resistor. An internal reference voltage is applied to a

resistor connected between R0 and R1 to set the operating current and

the cable driver output current. A low temperature-coefficient resistor

(TCR) with a value of 2.49 kΩ ± 1% should be used to meet the

IEEE 1394-1995 standard requirements for output voltage limits.

45

/RESET

I

Reset (Active-Low). When /RESET is asserted low (active), a bus reset

condition is set on the active cable ports and the internal logic is reset to

the reset start state. An internal pull-up resistor, which is connected to

VDD, is provided, so only an external delay capacitor in parallel with a

resistor is required to ensure that the capacitor is discharged when PHY

power is removed. This input is a standard logic buffer and can also be

driven by an open-drain logic output buffer.

23

SE

24

SM

I

Test Mode Control. SE is used during the manufacturing test and should

be tied to VSS.

I

Test Mode Control. SM is used during the manufacturing test and should

be tied to VSS.

* Active-low signals are indicated by “/” at the beginning of signal names, within this document.

Agere Systems Inc.

7

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