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FW801

One-Cable Transceiver/Arbiter Device

Agere -> LSI Corporation 

FW801 PHY IEEE 1394A

One-Cable Transceiver/Arbiter Device

Data Sheet, Rev. 1

June 2001

Table of Contents

Contents

Page

Distinguishing Features ............................................................................................................................................ 1

Features ................................................................................................................................................................... 1

Other Features ......................................................................................................................................................... 1

Description ................................................................................................................................................................ 1

Signal Information ..................................................................................................................................................... 6

Application Information .............................................................................................................................................9

1394 Application Support Contact Information .......................................................................................................10

Absolute Maximum Ratings ....................................................................................................................................11

Electrical Characteristics ........................................................................................................................................12

Timing Characteristics ............................................................................................................................................15

Timing Waveforms ..................................................................................................................................................16

Internal Register Configuration ...............................................................................................................................17

Outline Diagrams ....................................................................................................................................................22

List of Figures

Figure 1. Block Diagram .......................................................................................................................................... 5

Figure 2. Pin Assignments ....................................................................................................................................... 6

Figure 3. Typical External Component Connections ............................................................................................... 9

Figure 4. Typical Port Termination Network .......................................................................................................... 10

Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ............................................................ 16

Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms ...................................................................... 16

List of Tables

Table 1. Signal Descriptions ..................................................................................................................................... 6

Table 2. Absolute Maximum Ratings ......................................................................................................................11

Table 3. Analog Characteristics ..............................................................................................................................12

Table 4. Driver Characteristics ...............................................................................................................................13

Table 5. Device Characteristics ..............................................................................................................................14

Table 6. Switching Characteristics .........................................................................................................................15

Table 7. Clock Characteristics ................................................................................................................................15

Table 8. PHY Register Map for the Cable Environment ........................................................................................17

Table 9. PHY Register Fields for the Cable Environment ......................................................................................17

Table 10. PHY Register Page 0: Port Status Page ................................................................................................19

Table 11. PHY Register Port Status Page Fields ...................................................................................................20

Table 12. PHY Register Page 1: Vendor Identification Page ...............................................................................21

Table 13. PHY Register Vendor Identification Page Fields ....................................................................................21

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Agere Systems Inc.

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