ICS525-01RI 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS525-01RI Datasheet PDF : 9 Pages
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ICS525-01/02/11/12
User Configurable Clock
NOTE 1: Phase relationship between input and output can change at power-up. For a fixed phase
relationship, see the ICS527.
NOTE 2: For 16 MHz, 100 MHz output. Use the -02 for lowest jitter.
Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
28
INDEX
AREA
12
D
A
2
e
b
Millimeters
Inches*
E1 E
A
Symbol
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
Min
Max
1.35 1.75
0.10 0.25
--
1.50
0.20 0.30
0.18 0.25
9.80 10.00
5.80 6.20
3.80 4.00
0.635 Basic
0.40 1.27
0°
8°
--
0.10
Min
Max
.053 .069
.0040 .010
--
.059
.008 .012
.007 .010
.386 .394
.228 .244
.150 .157
0.025 Basic
.016 .050
0°
8°
--
0.004
*For reference only. Controlling dimensions in mm.
A
1
-C-
SEATING
PLANE
aaa C
c
L
MDS 525-01/02/11/12 Q
8
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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