MAX547 데이터 시트보기 (PDF) - Maxim Integrated
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MAX547 Datasheet PDF : 16 Pages
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Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
____________________________Typical Operating Characteristics (continued)
(VDD = 5V, VSS = -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA = +25°C, unless otherwise noted.)
ADJACENT-CHANNEL CROSSTALK
ADJACENT-CHANNEL CROSSTALK
A
5V/div
A:
5V/div
B
5mV/div
B:
5mV/div
500ns/div
REF– = 4.096V, CL = 50pF, RL = 10kΩ
A: DIGITAL INPUTS, DAC A, DATA BITS from ALL Os to OAAAhex
B: OUTPUT, DAC B
500ns/div
REF– = 4.096V, CL = 50pF, RL = 10kΩ
A: DIGITAL INPUTS, DAC A, DATA BITS from OAAAhex to ALL Os
B: OUTPUT, DAC B
______________________________________________________________Pin Description
PIN
PLCC
FLAT
PACK
NAME
FUNCTION
1
2
3
4, 42
5
6
7
8
9, 37
10
11
12
39
–C—L—R–
40 AGNDCD
41
REFCD
42, 36
VSS
43
VOUTD
44
VOUTC
1
VOUTB
2
VOUTA
3, 31
VDD
4
REFAB
5
AGNDAB
6
L–—D—A—B–
Clear Input (active low). Driving this asynchronous input low sets the content of all latches to
1000hex. All DAC outputs are reset to AGND_.
Analog Ground for DAC C and DAC D
Reference Voltage Input for DAC C and DAC D. Bypass to AGNDCD with a 0.1µF to 1µF capacitor.
Negative Power Supply, -5V (2 pins). Connect both pins to the supply voltage. Bypass each pin
to the system analog ground with a 0.1µF to 1µF capacitor.
DAC D Output Voltage
DAC C Output Voltage
DAC B Output Voltage
DAC A Output Voltage
Positive Power Supply, 5V (2 pins). Connect both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1µF to 1µF capacitor.
Reference Voltage Input for DAC A and DAC B. Bypass to AGNDAB with a 0.1µF to 1µF capacitor.
Analog Ground for DAC A and DAC B
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
A and B to the respective DAC latches.
13
7
–L—D—C—D–
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
C and D to the respective DAC latches.
14
8
15
9
–C—S–
Chip Select (active low)
W–—R–
Write Input (active low). –W—R–, along with –C—S–, loads data into the DAC input latch selected by A0–A2.
6 _______________________________________________________________________________________
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