HMP8156ACN 데이터 시트보기 (PDF) - Intersil

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HMP8156ACN

NTSC/PAL Encoders

Intersil 

HMP8154, HMP8156A

BIT

NUMBER

FUNCTION

7-0

Field Detect

Window Size Low

TABLE 29. FIELD CONTROL REGISTER 1

SUB ADDRESS = 26H

DESCRIPTION

This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect

Window Size value. The value specifies the number of 1X clock cycles in the detection window

before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge

of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the

FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured

as inputs.

RESET

STATE

80H

BIT

NUMBER

FUNCTION

7-4

Half Line Count

Reset Value

2

VSYNC Edge

Select

1

FIELD Detect

Select

0

Field Detect

Window Size High

TABLE 30. FIELD CONTROL REGISTER 2

SUB ADDRESS = 27H

DESCRIPTION

RESET

STATE

These bits specify the value to load to the vertical half line counter when the selected edge of

VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.

This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine

the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are config-

ured as inputs.

0 = leading edge

1 = trailing edge

This bit specifies whether an odd or even field is starting when the leading edge of HSYNC

occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are config-

ured as inputs.

0 = odd field

1 = even field

This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size

value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.

00000B

0B

0B

0B

23

4343.4

November 4, 2005

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