DESCRIPTION
The SY100S302 offers five 2-input OR/NOR gates designed for use in high-performance ECL systems. The five gates are controlled by a common Enable signal. All inputs have 75KΩ pull-down resistors and all outputs are buffered.

FEATURES
■ Max. propagation delay of 700ps
■ IEE min. of –45mA
■ Industry standard 100K ECL levels
■ Extended supply voltage option: VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved noise immunity
■ Internal 75KΩ input pull-down resistors
■ 50% faster than Fairchild 300K
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC packages