Device Highlights
Flexible Programmable Logic
0.18 µm six layer metal CMOS Process
1.8/2.5/3.3 V Drive Capable I/O
960 Logic Cells
248,160 Max System Gates
Up to 250 I/O Pins

Embedded Dual Port SRAM
Twenty 2,304-bit Dual Port High Performance SRAM Blocks
46,100 RAM bits
RAM/ROM/FIFO Wizard for Automatic Configuration
Configurable and Cascadable

Programmable I/O
High performance Enhanced I/O (EIO)—less than 3 ns Tco
Programmable Slew Rate Control
Programmable I/O Standards:
  LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3
  Eight Independent I/O Banks
  Three Register Configurations: Input, Output, and Output Enable

Advanced Clock Network
Nine Global Clock Networks:
  One Dedicated
  Eight Programmable
20 Quad-Net Networks—five per Quadrant
16 I/O Controls—two per I/O Bank
Four phase locked loops