PRODUCT SUMMARY
The QL2007 is a 7,000 usable ASIC gate, 11,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.

FEATURES
■ Total of 174 I/O Pins
   - 166 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades
   - 4 high-drive input-only pins
   - 4 high-drive input/distributed network pins
■ Four Low-Skew (less than 0.5ns) Distributed Networks
   - Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin
   - Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback
■ High Performance
   - Input + logic cell + output delays under 6 ns
   - Datapath speeds exceeding 225 MHz
   - Counter speeds over 200 MHz