High-Performance RISC CPU:
• C Compiler Optimized Architecture
• 256 bytes Data EEPROM
• Up to 14 Kbytes Linear Program Memory Addressing
• Up to 1024 bytes Linear Data Memory Addressing
• Interrupt Capability with Automatic Context Saving
• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory