DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO mode fuction, fabricated with the high performance CMOS process, and is ideal for the buffer memory systems of personal computer graphics and HDD where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. The lower supply (3.3V) operation, due to the optimization of transistor structure, provides low power dissipation while maintaining high speed operation. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application. This device has 2CAS and 1W terminals with a refresh cycle of 512 cycles every 8.2ms.

FEATURES
● Standard 40 pin SOJ, 44 pin TSOP (II)
● Single 3.3±0.3V supply
● Low stand-by power dissipation
   CMOS Input level ------------------------------ 1.8mW (Max)
   CMOS Input level ------------------------------ 360µW (Max) *
● Operating power dissipation
   M5M4V4265CXX-5,-5S  --------------------------- 486mW (Max)
   M5M4V4265CXX-6,-6S  --------------------------- 432mW (Max)
   M5M4V4265CXX-7,-7S  --------------------------- 396mW (Max)
● Self refresh capability *
   Self refresh current  ------------------------- 100µA (Max)
● Extended refresh capability
   Extended refresh current  --------------------- 100µA (Max)
● EDO mode (512-column random access), Read-modify-write, RASonly refresh, CAS before RAS refresh, Hidden refresh capabilities.
● Early-write mode, OE and W to control output buffer impedance
● 512 refresh cycles every 8.2ms (A0~A8)
● 512 refresh cycles every 128ms (A0~A8) *
● Byte or word control for Read/Write operation (2CAS, 1W type)
  * : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S, -7S : option) only

APPLICATION
   Microcomputer memory, Refresh memory for CRT, Frame buffer memory for CRT