HYB5117405BJ-500 データシート, Siemens AG HYB5117405BJ-500 PDF

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HYB5117405BJ-500 データシート - Siemens AG

部品番号

HYB5117405BJ-500

コンポーネント説明

4M x 4-Bit Dynamic RAM 2k & 4k Refresh (Hyper Page Mode- EDO)

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28 Pages

File Size

280.9 kB

メーカー

Siemens AG

Advanced Information
• 4 194 304 words by 4-bit organization
• 0 to 70 °C operating temperature
• Performance:
• Single + 5 V (± 10 %) supply
• Low power dissipation
    max. 550 mW active (HYB5116405BJ/BT-50)
    max. 495 mW active (HYB5116405BJ/BT-60)
    max. 440 mW active (HYB5116405BJ/BT-70)
    max. 660 mW active (HYB5117405BJ/BT-50)
    max. 605 mW active (HYB5117405BJ/BT-60)
    max. 550 mW active (HYB5117405BJ/BT-70)
    11 mW standby (TTL)
    5.5. mW standby (MOS)
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode
• Hyper page mode (EDO) capability
• All inputs, outputs and clocks fully TTL-compatible
• 4096 refresh cycles / 64 ms for HYB5116405BJ/BT (4k-Refresh)
• 2048 refresh cycles / 32 ms for HYB5117405BJ/BT (2k-Refresh)
• Plastic Package: P-SOJ-26/24 300 mil P TSOPII-26/24 300 mil