Functional Description
The GS8322Z18/36/72 is a 36Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

FEATUREs
• NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119- or 209-Bump BGA package