CP208(2002) データシート - Central Semiconductor
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Central Semiconductor
PROCESS DETAILS
Process EPITAXIAL PLANAR
Die Size 66 x 66 MILS
Die Thickness 12.5 ± 1.0 MILS
Base Bonding Pad Area 12 x 24 MILS
Emitter Bonding Pad Area 11 x 14 MILS
Top Side Metalization Al - 50,000Å
Back Side Metalization Cr/Ni/Ag - 16,000Å
Power Transistor NPN - Amp/Switch Transistor Chip
Central Semiconductor
Power Transistor NPN - Amp/Switch Transistor Chip
Central Semiconductor
Power Transistor NPN - Amp/Switch Transistor Chip ( Rev : 2004 )
Central Semiconductor
Power Transistor NPN - Amp/Switch Transistor Chip
Central Semiconductor
Power Transistor PNP - Amp/Switch Transistor Chip
Central Semiconductor
Power Transistor PNP - Amp/Switch Transistor Chip
Central Semiconductor
Power Transistor PNP - Amp/Switch Transistor Chip
Central Semiconductor Corp
Power Transistor PNP - Amp/Switch Transistor Chip ( Rev : 2003 )
Central Semiconductor
Power Transistor PNP - Amp/Switch Transistor Chip
Central Semiconductor
Small Signal Transistor NPN - Amp/Switch Transistor Chip ( Rev : 2002 )
Central Semiconductor