General Description
ProASICPLUS devices offer a reprogrammable design integration solution at the automotive temperature range (-40°C to +125°C) through the use of nonvolatile Flash technology. ProASICPLUS devices have a fine-grain architecture, similar to ASICs, and enable engineers to design high-density systems using existing ASIC or FPGA design flows and tools. Automotive-grade ProASICPLUS devices offer up to 1 million system gates, support up to 198kbits of two-port SRAM and 642 user I/Os and provide 50 MHz PCI performance.

FEATUREs and Benefits
High Capacity
    • 75,000 to 1 Million System Gates
    • 27k to 198kbits of Two-Port SRAM
    • 66 to 642 User I/Os
Reprogrammable Flash Technology
    • 0.22µ 4LM Flash-based CMOS Process
    • Live at Power-Up, Single-Chip Solution
    • No Configuration Device Required
    • Retains Programmed Design during Power-Down/Power-Up Cycles
Extended Temperature Range
    • Supports Automotive Temperature Range -40 to 125°C (Junction)
Performance
    • 3.3V, 32-Bit PCI (up to 50 MHz)
    • Two Integrated PLLs
    • External System Performance up to 150 MHz
Secure Programming
    • Industry’s Most Effective Security Key (FlashLock™) Prevents Read Back of Programming Bitstream
Low Power
    • Low Impedance Flash Switches
    • Segmented Hierarchical Routing Structure
    • Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells
High Performance Routing Hierarchy
    • Ultra-Fast Local and Long-Line Network
    • High-Speed, Very Long-Line Network
    • High Performance, Low-Skew, Splittable Global Network
    • 100% Utilization and >95% Routability
I/O
    • Schmitt-Trigger Option on Every Input
    • 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate
    • Bidirectional Global I/Os
    • Compliance with PCI Specification Revision 2.2
    • Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
    • Pin Compatible Packages across ProASICPLUS Family
Unique Clock Conditioning Circuitry
    • PLLs with Flexible Phase, Multiply/Divide and Delay Capabilities
    • Internal and/or External Dynamic PLL Configuration
    • Two LVPECL Differential Pairs for Clock or Data Inputs
Standard FPGA and ASIC Design Flow
    • Flexibility with Choice of Industry-Standard Frontend Tools
    • Efficient Design through Front-End Timing and Gate Optimization
ISP Support
    • In-System Programming (ISP) via JTAG Port
SRAMs and FIFOs
    • ACTgen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks
    • 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical)