部品番号
74VHC126
コンポーネント説明
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Nexperia B.V. All rights reserved
74VHC126 データシート - Nexperia B.V. All rights reserved
Nexperia B.V. All rights reserved
General description
The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A.
The 74VHC126; 74VHCT126 provide four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state.
The 74VHC126; 74VHCT126 are identical to the 74VHC125; 74VHCT125 but have active HIGH output enable inputs.
Features
• Balanced propagation delays
• All inputs have Schmitt-trigger action
• Inputs accept voltages higher than VCC
• Input levels:
• The 74VHC126 operates with CMOS input level
• The 74VHCT126 operates with TTL input level
• ESD protection:
• HBM JESD22-A114E exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• CDM JESD22-C101C exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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