部品番号
74ALVC00BQ-Q100
コンポーネント説明
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74ALVC00BQ-Q100 データシート - Nexperia B.V. All rights reserved
Nexperia B.V. All rights reserved
General description
The 74ALVC00-Q100 is a quad 2-input NAND gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 1.65 V to 3.6 V
• CMOS low power dissipation
• Overvoltage tolerant inputs to 3.6 V
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 250 mA per JESD78 Class II.A
• Complies with JEDEC standards:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
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