datasheetbank_Logo
データシート検索エンジンとフリーデータシート
HOME  >>>  Data Delay Devices  >>> 3D3521H PDF

3D3521H データシート - Data Delay Devices

3D3521H image

部品番号
3D3521H

コンポーネント説明

Other PDF
  no available.

PDF
DOWNLOAD     

page
4 Pages

File Size
153.6 kB

メーカー
DATADIELAY
Data Delay Devices 

FUNCTIONAL DESCRIPTION
The 3D3521 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi-phaselevel signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. The unit operating baud rate (in Mbaud) is equal to the input clock frequency (in MHZ). All pins marked N/C must be left unconnected.


FEATURES
• All-silicon, low-power CMOS technology
• 3.3V operation
• CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Maximum data rate: 50 MBaud

Page Link's: 1  2  3  4 

部品番号
コンポーネント説明
ビュー
メーカー
MONOLITHIC MANCHESTER ENCODER
PDF
Data Delay Devices
MONOLITHIC MANCHESTER ENCODER
PDF
Data Delay Devices
MONOLITHIC MANCHESTER ENCODER/DECODER
PDF
Data Delay Devices
MONOLITHIC MANCHESTER ENCODER/DECODER
PDF
Data Delay Devices
MONOLITHIC MANCHESTER ENCODER/DECODER
PDF
Data Delay Devices
Manchester Encoder / Decoder ( Rev : 2001 )
PDF
Holt Integrated Circuits
CMOS Manchester Encoder-Decoder
PDF
Intersil
CMOS Manchester Encoder / Decoder
PDF
Aeroflex Corporation
MANCHESTER ENCODER/DECODER MODULES
PDF
Unspecified
CMOS Manchester Encoder-Decoder
PDF
Intersil

Share Link: GO URL

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]