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2N5564-E3 データシート - Vishay Semiconductors

2N5564-E3 image

部品番号
2N5564-E3

コンポーネント説明

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6 Pages

File Size
83.4 kB

メーカー
Vishay
Vishay Semiconductors 

DESCRIPTION
The 2N5564/5565/5566 are matched pairs of JFETs mounted in a TO-71 package. This two-chip design reduces parasitics for good performance at high frequency while ensuring extremely tight matching. This series features high breakdown voltage (V(BR)DSS typically > 55 V), high gain (typically > 9 mS), and <5 mV offset between the two die.


FEATURES
● Two-Chip Design
● High Slew Rate
● Low Offset/Drift Voltage
● Low Gate Leakage: 3 pA
● Low Noise: 12 nV⁄√Hz @ 10 Hz
● Good CMRR: 76 dB
● Minimum Parasitics


BenefitS
● Tight Differential Match vs. Current
● Improved Op Amp Speed, Settling Time Accuracy
● Minimum Input Error/Trimming Requirement
● Insignificant Signal Loss/Error Voltage
● High System Sensitivity
● Minimum Error with Large Input Signals
● Maximum High Frequency Performance


APPLICATIONS
● Wideband Differential Amps
● High-Speed, Temp-Compensated, Single-Ended Input Amps
● High-Speed Comparators
● Impedance Converters
● Matched Switches

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