UPD705100 データシートの表示（PDF） - NEC => Renesas Technology

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UPD705100

V830™ 32-BIT MICROCONTROLLER

NEC => Renesas Technology 

µPD705100

(b) When the internal operating frequency is 48 to 100 MHz

Parameter

Symbol

Address output delay

14

(relative to BCLK↑)

Address output hold time

15

(relative to BCLK↑)

CSn output delay (relative to BCLK↑) 16

tDKA

tHKA

tDKCS

CSn output hold time

17

(relative to BCLK↑)

BCYST output delay

18

(relative to BCLK↑)

BCYST output hold time

19

(relative to BCLK↑)

READY set time (relative to BCLK↑) 20

tHKCS

tDKBC

tHKBC

tSRYK

READY hold time (relative to BCLK↑) 21 tHKRY

Data set time (relative to BCLK↑) 22 tSDK

Data hold time (relative to BCLK↑) 23 tHKD

Data output delay

(from active, relative to BCLK↑)

Data output hold time

(to active, relative to BCLK↑)

Data output delay

(from float, relative to BCLK↑)

Data output hold time

(to float, relative to BCLK↑)

24 tDKDT

25 tHKDT

26 tLZKDT

27 tHZKDT

Conditions

When φ = 3f

When φ = 2f

Unit

MIN. MAX. MIN. MAX.

1

13

1

13

ns

1

13

1

13

ns

1

13

1

13

ns

1

13

1

13

ns

1

13

1

13

ns

1

13

1

13

ns

10

10

ns

0

0

ns

7

7

ns

2

1

ns

1

13

1

13

ns

1

13

1

13

ns

1

13

1

13

ns

3

20

3

20

ns

51

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