AD7847BNN データシートの表示（PDF） - Analog Devices

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AD7847BNN

LC2MOS Complete, Dual 12-Bit MDACs

Analog Devices 

AD7837/AD7847

CIRCUIT INFORMATION

D/A SECTION

A simplified circuit diagram for one of the D/A converters and

output amplifier is shown in Figure 10.

A segmented scheme is used whereby the 2 MSBs of the 12-bit

data word are decoded to drive the three switches A-C. The

remaining 10 bits drive the switches (S0–S9) in a standard R-2R

ladder configuration.

Each of the switches A–C steers 1/4 of the total reference cur-

rent with the remaining 1/4 passing through the R-2R section.

The output amplifier and feedback resistor perform the current

to voltage conversion giving

VOUT = – D × VREF

where D is the fractional representation of the digital word. (D

can be set from 0 to 4095/4096.)

The output amplifier can maintain ± 10 V across a 2 kΩ load. It

is internally compensated and settles to 0.01% FSR (1/2 LSB)

in less than 5 µs. Note that on the AD7837, VOUT must be con-

nected externally to RFB.

VREF

R

R

R

2R 2R 2R 2R 2R

C

B

A

S9 S8

2R 2R

S0

R /2

VOUT

SHOWN FOR ALL 1s ON DAC

AGND

Figure 10. D/A Simplified Circuit Diagram

INTERFACE LOGIC INFORMATION—AD7847

The input control logic for the AD7847 is shown in Figure 11.

The part contains a 12-bit latch for each DAC. It can be treated

as two independent DACs, each with its own CS input and a com-

mon WR input. CSA and WR control the loading of data to the

DAC A latch, while CSB and WR control the loading of the

DAC B latch. The latches are edge triggered so that input data

is latched to the respective latch on the rising edge of WR. If CSA

and CSB are both low and WR is taken high, the same data will

be latched to both DAC latches. The control logic truth table is

shown in Table I, while the write cycle timing diagram for the

part is shown in Figure 12.

CSA

WR

DAC A LATCH

CSB

DAC B LATCH

Figure 11. AD7847 Input Control Logic

Table I. AD7847 Truth Table

CSA CSB

WR

Function

X

X

1

1

0

1

1

0

0

0

g

1

1

g

g

g

1

No Data Transfer

X

No Data Transfer

g

Data Latched to DAC A

g

Data Latched to DAC B

g

Data Latched to Both DACs

0

Data Latched to DAC A

0

Data Latched to DAC B

0

Data Latched to Both DACs

X = Don’t Care. g = Rising Edge Triggered.

CSA, CSB

WR

DATA

t1

t3

t2

t4

t5

VALID

DATA

Figure 12. AD7847 Write Cycle Timing Diagram

INTERFACE LOGIC INFORMATION—AD7837

The input loading structure on the AD7837 is configured for

interfacing to microprocessors with an 8-bit-wide data bus. The

part contains two 12-bit latches per DAC—an input latch and

a DAC latch. Each input latch is further subdivided into a least-

significant 8-bit latch and a most-significant 4-bit latch. Only the

data held in the DAC latches determines the outputs from the part.

The input control logic for the AD7837 is shown in Figure 13,

while the write cycle timing diagram is shown in Figure 14.

LDAC

CS

WR

A0

A1

DAC A

LATCH

DAC B

LATCH

12

12

4

DAC A MS

INPUT

LATCH

8

DAC A LS

INPUT

LATCH

4

DAC B LS

INPUT

LATCH

8

DAC B LS

INPUT

LATCH

8

DB7 DB0

Figure 13. AD7837 Input Control Logic

REV. C

–7–

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