ADM1068
Preliminary Technical Data
1
91
9
SCL
SDA
1 0 0 0 1 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
START BY
MASTER
ACK. BY
SLAVE
ACK. BY
MASTER
FRAME 1
FRAME 2
SLAVE ADDRESS
DATA BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 3
DATA BYTE
ACK. BY
MASTER
D7 D6 D5 D4 D3 D2 D1 D0
FRAME N
DATA BYTE
STOP
NO ACK.
BY
MASTER
Figure 26. General SMBus Read Timing Diagram
SCL
SDA
tBUF
PS
tR
tLOW
t HD; STA
tHD;DAT
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
tSU;STO
S
P
SMBus Protocols for RAM and EEPROM
Figure 27. Serial Bus Timing Diagram
The ADM1068 contains volatile registers (RAM) and nonvola-
tile registers (EEPROM). User RAM occupies address locations
from 0x00 to 0xDF; EEPROM occupies addresses from 0xF800
to 0xFBFF.
Data can be written to and read from both RAM and EEPROM
as single data bytes. Data can be written only to unprogrammed
EEPROM locations. To write new data to a programmed loca-
tion, it must first be erased. EEPROM erasure cannot be done at
the byte level. The EEPROM is arranged as 32 pages of 32 bytes
each, and an entire page must be erased.
The ADM1068 uses the following SMBus write protocols.
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in the diagrams:
S Start
P Stop
R Read
W Write
A Acknowledge
A No acknowledge
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
In the ADM1068, the send byte protocol is used for two
purposes:
• To write a register address to RAM for a subsequent single
byte read from the same address, or a block read or write
starting at that address, as shown in Figure 28.
1
2
S
SLAVE
ADDRESS
3
WA
4
REGISTER
ADDRESS
(0x00 TO 0xDF)
56
AP
Figure 28. Setting a RAM Address for Subsequent Read
Rev. PrB | Page 22 of 28