ADSP-21371/ADSP-21375
Reset
Table 15. Reset
Parameter
Min
Max
Unit
Timing Requirements
tWRST1
RESET Pulse Width Low
4 × tCK
ns
tSRST
RESET Setup Before CLKIN Low
8
ns
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
RESET
tWRST
Figure 8. Reset
Running Reset
The following timing specification applies to
RESETOUT/RUNRSTIN pin when it is configured as
RUNRSTIN.
Table 16. Running Reset
Parameter
Timing Requirements
tWRUNRST
tSRUNRST
Running RESET Pulse Width Low
Running RESET Setup Before CLKIN High
Min
4 × tCK
8
tSRST
Max
Unit
ns
ns
CLKIN
RUNRSTIN
tWRUNRST
tSRUNRST
Figure 9. Running Reset
Rev. C | Page 21 of 52 | September 2009