LTC2298I データシートの表示（PDF） - Linear Technology

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LTC2298I

Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs

Linear Technology 

LTC2298/LTC2297/LTC2296

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2296: SFDR vs Input Level,

fIN = 5MHz, 2V Range, 25Msps

120

110

100

dBFS

90

80

dBc

70

60

90dBc SFDR

REFERENCE LINE

50

40

30

20

–60

–50 –40 –30 –20

INPUT LEVEL (dBFS)

–10 0

2296 G13

LTC2296: IVDD vs Sample Rate,

5MHz Sine Wave Input, –1dB

70

60

2V RANGE

50

1V RANGE

40

30

0 5 10 15 20 25 30 35

SAMPLE RATE (Msps)

2296 G14

LTC2296: IOVDD vs Sample Rate,

5MHz Sine Wave Input, –1dB,

OVDD = 1.8V

6

4

2

0

0 5 10 15 20 25 30 35

SAMPLE RATE (Msps)

2296 G15

PI FU CTIO S

AINA+ (Pin 1): Channel A Positive Differential Analog

Input.

AINA– (Pin 2): Channel A Negative Differential Analog

Input.

REFHA (Pins 3, 4): Channel A High Reference. Short

together and bypass to Pins 5, 6 with a 0.1µF ceramic chip

capacitor as close to the pin as possible. Also bypass to

Pins 5, 6 with an additional 2.2µF ceramic chip capacitor

and to ground with a 1µF ceramic chip capacitor.

REFLA (Pins 5, 6): Channel A Low Reference. Short

together and bypass to Pins 3, 4 with a 0.1µF ceramic chip

capacitor as close to the pin as possible. Also bypass to

Pins 3, 4 with an additional 2.2µF ceramic chip capacitor

and to ground with a 1µF ceramic chip capacitor.

VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to

GND with 0.1µF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input sample

starts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input sample

starts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Short

together and bypass to Pins 13, 14 with a 0.1µF ceramic

chip capacitor as close to the pin as possible. Also bypass

to Pins 13, 14 with an additional 2.2µF ceramic chip ca-

pacitor and to ground with a 1µF ceramic chip capacitor.

REFHB (Pins 13, 14): Channel B High Reference. Short

together and bypass to Pins 11, 12 with a 0.1µF ceramic

chip capacitor as close to the pin as possible. Also bypass

to Pins 11, 12 with an additional 2.2µF ceramic chip ca-

pacitor and to ground with a 1µF ceramic chip capacitor.

AINB– (Pin 15): Channel B Negative Differential Analog

Input.

AINB+ (Pin 16): Channel B Positive Differential Analog

Input.

GND (Pins 17, 64): ADC Power Ground.

SENSEB (Pin 19): Channel B Reference Programming Pin.

Connecting SENSEB to VCMB selects the internal reference

and a ±0.5V input range. VDD selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEB selects an input

range of ±VSENSEB. ±1V is the largest valid input range.

VCMB (Pin 20): Channel B 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2µF ceramic chip

capacitor. Do not connect to VCMA.

229876fa

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