ST72F325K(2007) データシートの表示（PDF） - STMicroelectronics

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ST72F325K
(Rev.:2007)

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

STMicroelectronics 

LD sema,A

IRET

Case 2: Writing to PxOR or PxDDR with Global In-

terrupts Disabled:

SIM

; set the interrupt mask

LD A,PFDR

AND A,#$02

LD X,A ; store the level before writing to

PxOR/PxDDR

LD A,#$90

LD PFDDR,A; Write into PFDDR

LD A,#$ff

LD PFOR,A

; Write to PFOR

LD A,PFDR

AND A,#$02

LD Y,A

PxDDR

; store the level after writing to PxOR/

LD A,X ; check for falling edge

cp A,#$02

jrne OUT

TNZ Y

jrne OUT

LD A,#$01

LD sema,A ; set the semaphore to '1' if edge is

detected

RIM

; reset the interrupt mask

LD A,sema ; check the semaphore status

CP A,#$01

jrne OUT

call call_routine; call the interrupt routine

RIM

OUT:

RIM

JP while_loop

.call_routine ; entry to call_routine

PUSH A

PUSH X

PUSH CC

.ext1_rt ; entry to interrupt routine

LD A,#$00

LD sema,A

IRET

15.1.3 Clearing active interrupts outside

interrupt routine

When an active interrupt request occurs at the

same time as the related flag is being cleared, an

unwanted reset may occur.

Note: clearing the related interrupt mask will not

generate an unwanted reset

Concurrent interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

Perform SIM and RIM operation before and after

resetting an active interrupt request.

Example:

SIM

reset interrupt flag

RIM

Nested interrupt context:

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine with higher or identical priority level

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

PUSH CC

SIM

reset interrupt flag

POP CC

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