IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J
BLOCK DIAGRAM
®
ISSI
CLK
ADV
ADSC
ADSP
A
GW
BWE
BWd
(x32/x36)
BWc
(x32/x36)
BWb
(x32/x36/x18)
BWa
(x32/x36/x18)
CE (T,D)
CE2 (T,D)
CE2 (T)
OE
18/19
MODE
CLK
Q0 A0
A0'
BINARY
COUNTER
CE
Q1 A1
A1'
CLR
D
Q
ADDRESS
REGISTER
CE
CLK
16/17
256Kx32; 256Kx36;
512Kx18
MEMORY ARRAY
18/19
32, 36,
or 18
32, 36,
or 18
D DQd Q
BYTE WRITE
REGISTERS
CLK
D DQc Q
BYTE WRITE
REGISTERS
CLK
D DQb Q
BYTE WRITE
REGISTERS
CLK
D DQa Q
BYTE WRITE
REGISTERS
CLK
D
Q
ENABLE
REGISTER
CE
CLK
4
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
32, 36,
or 18
DQa - DQd
OE
D
Q
ENABLE
DELAY
REGISTER
CLK
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
04/29/02