EVAL-AD7864-2CB データシートの表示（PDF） - Analog Devices
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EVAL-AD7864-2CB Datasheet PDF : 28 Pages
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AD7864
TIMING CHARACTERISTICS
VDRIVE = 5 V± 5%, AGND = DGND = 0 V, VREF = internal, clock = internal; all specifications TMIN to TMAX, unless otherwise noted.1, 2
Table 2.
Parameter
tCONV
tACQ
tBUSY
tWAKE-UP —External VREF
tWAKE-UP —Internal VREF3
t1
t2
READ OPERATION
t3
t4
t5
t6 4
t7 5
t8
t9
t10
t11
t12
WRITE OPERATION
t13
t14
t15
t16
t17
A, B Versions
1.65
13
2.6
0.34
No. of channels ×
(tCONV + t9) − t9
2
6
35
70
0
0
35
40
35
40
5
30
10
75
180
70
15
0
20
0
0
5
5
Unit
μs max
Clock cycles
μs max
μs max
μs max
μs max
ms max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
Conversion time, internal clock
Conversion time, external clock
CLKIN = 5 MHz
Acquisition time
Selected number of channels multiplied by (tCONV + EOC pulse
width)—EOC pulse width
STBY rising edge to CONVST rising edge
STBY rising edge to CONVST rising edge
CONVST pulse width
CONVST rising edge to BUSY rising edge
CS to RD setup time
CS to RD hold time
Read pulse width, VDRIVE = 5 V
Read pulse width, VDRIVE = 3 V
Data access time after falling edge of RD, VDRIVE = 5 V
Data access time after falling edge of RD, VDRIVE = 3 V
Bus relinquish time after rising edge of RD
Time between consecutive reads
EOC pulse width
RD rising edge to FRSTDATA edge (rising or falling)
EOC falling edge to FRSTDATA falling delay
EOC to RD delay
WR pulse width
CS to WR setup time
WR to CS hold time
Input data setup time of rising edge of WR
Input data hold time
1 Sample tested at initial release to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2 See Figure 9, Figure 10,and Figure 11.
3 Refer to the Standby Mode Operation section. The maximum specification of 6 ms is valid when using a 0.1 μF decoupling capacitor on the VREF pin.
4 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is
then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part, and as such, are independent of external bus loading capacitances.
1.6mA
TO
OUTPUT
50pF
400µA
1.6V
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
Rev. D | Page 5 of 28
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