CY7C1441AV25-133AXI データシートの表示（PDF） - Cypress Semiconductor
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CY7C1441AV25-133AXI Datasheet PDF : 31 Pages
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Pin Definitions (continued)
Name
DQPX
I/O
I/O-
Synchronous
MODE
Input-Static
VDD
VDDQ
VSS
VSSQ
TDO
TDI
TMS
TCK
Power Supply
I/O Power Supply
Ground
I/O Ground
JTAG serial output
Synchronous
JTAG serial
input
Synchronous
JTAG serial
input
Synchronous
JTAG-Clock
NC
-
NC/72M, NC/144M,
-
NC/288M, NC/576M
NC/1G
Description
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical
to DQs. During write sequences, DQPx is controlled by BW[A:H] correspond-
ingly.
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to VDD or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation. Mode Pin has an internal
pull-up.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the core of the device.
Ground for the I/O circuitry.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK. If the JTAG feature is not being utilized, this pin should be left uncon-
nected. This pin is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin can be left floating or connected to
VDD through a pull up resistor. This pin is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin can be disconnected or connected
to VDD. This pin is not available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized,
this pin must be connected to VSS. This pin is not available on TQFP
packages.
No Connects. Not internally connected to the die. 72M, 144M and 288M are
address expansion pins are not internally connected to the die.
No Connects. Not internally connected to the die. NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally
connected to the die.
Document #: 38-05357 Rev. *F
Page 8 of 31
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