CY7C1442AV33(2005) データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C1442AV33 Datasheet PDF : 27 Pages
| |||
PRELIMINARY
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Thermal Resistance[20]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Capacitance[20]
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA / JESD51.
100 TQFP
Package
25.21
2.28
Parameter
Description
CIN
CCLK
CI/O
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
100 TQFP
Package
6.5
3
5.5
165 BGA
Package
20.8
3.2
165 BGA
Package
5
5
7
209 fBGA
Package
25.31
4.48
209 fBGA
Package
5
5
7
Unit
°C/W
°C/W
Unit
pF
pF
pF
3.3V I/O Test Load
OUTPUT
Z0 = 50Ω
3.3V
OUTPUT
RL = 50Ω
5 pF
VT = 1.5V
(a)
2.5V I/O Test Load
INCLUDING
JIG AND
SCOPE
OUTPUT
2.5V
Z0 = 50Ω
OUTPUT
RL = 50Ω
5 pF
INCLUDING
VT = 1.25V
(a)
JIG AND
SCOPE
R = 317Ω
R = 351Ω
VDDQ
GND
ALL INPUT PULSES
10%
90%
≤ 1 ns
90%
10%
≤ 1 ns
(b)
(c)
R = 1667Ω
R = 1538Ω
VDDQ
GND
10%
≤ 1 ns
ALL INPUT PULSES
90%
90%
10%
≤ 1 ns
(b)
(c)
Switching Characteristics Over the Operating Range [25, 26]
250 MHz
200 MHz
167 MHz
Parameter
tPOWER
Clock
Description
VDD(Typical) to the first Access[21]
Min. Max Min. Max. Min. Max Unit
1
1
1
ms
tCYC
tCH
tCL
Output Times
Clock Cycle Time
Clock HIGH
Clock LOW
4.0
5
6
ns
1.5
2.0
2.4
ns
1.5
2.0
2.4
ns
tCO
Data Output Valid After CLK Rise
2.6
3.2
3.4
ns
tDOH
tCLZ
Data Output Hold After CLK Rise
Clock to Low-Z[22, 23, 24]
1.0
1.5
1.5
ns
1.0
1.3
1.5
ns
Notes:
20. Tested initially and after any design or process change that may affect these parameters.
21. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
22. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
23. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
24. This parameter is sampled and not 100% tested.
25. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
26. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05383 Rev. *B
Page 19 of 27
Share Link: 