CY7C1442AV33(2005) データシートの表示（PDF） - Cypress Semiconductor
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CY7C1442AV33 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
TAP AC Switching Characteristics Over the operating Range[11, 12]
Parameter
Description
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
tTL
TCK Clock LOW time
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
tTDIS
TDI Set-up to TCK Clock Rise
tCS
Capture Set-up to TCK Rise
Hold Times
tTMSH
tTDIH
tCH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
Min.
50
25
25
0
5
5
5
5
5
5
Max.
20
5
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ............................................... VSS to 3.3V
Input rise and fall times ...................... ..............................1ns
Input timing reference levels ...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels................................................ .VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
1.5V
2.5V TAP AC Output Load Equivalent
1.25V
TDO
ZO= 50Ω
50Ω
20pF
TDO
ZO= 50Ω
50Ω
20pF
Notes:
11.
t
CS
and
tCH
refer
to
the
set-up
and
hold
time
requirements
of
latching
data
from
the
boundary
scan
register.
12. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = ns.
Document #: 38-05383 Rev. *B
Page 14 of 27
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