ADP3088ARM-REEL データシートの表示（PDF） - Analog Devices

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ADP3088ARM-REEL

1 MHz, 750 mA Buck Regulator

Analog Devices 

ADP3088

2.5 V system voltage to the FB node that will reduce the out- The design of either parallel bit or PWM type of voltage control

put voltage according to the formula

must consider whether the interface node(s), from parallel

( ) DVOUT = VREF -VTT

RA

RTT

(19)

Dynamic Voltage Control

Some newer power management applications also require an

ability to adjust the voltage being delivered to a load during

operation. Although there is no integration of this feature in the

ADP3088, it can readily be accommodated with a few compo-

nents. Dynamic voltage control can be implemented either by

parallel bus control or by PWM. In both cases, the output voltage

switched bits or a single PWM signal, has an active pull-up state

(in which case it must be to a known voltage) or a passive pull-up

(open drain) that floats up to the FB node voltage, 1.25 V, in its

high state. If at least the lower extreme of the desired output

voltage range must be lower than 1.25 V, either technique can

be combined with the technique for lowering the output voltage

below 1.25 V. Such an example of an application having this

requirement is the Blackfin® DSP. Figure 5 shows an implementa-

tion of this technique.

Input Voltage: 4.75 V ~ 7.5 V

is modified by summing either switched bits with, presumably

binary, weighting resistors or a switched PWM node via a single

resistor into the FB pin. (The switched PWM node refers to an

external PWM control signal, not the switched node of the power

converter itself.) Since the PWM technique modulates a current

into the FB node, it is necessary both to integrate that signal

E and to avoid slowing down the response of the power converter

to the output voltage transitions. This can be accomplished by

placing a capacitor between the output voltage and the feedback

node, which serves to provide a zero/pole pair in the main regu-

T lation loop and appears as an integration pole to the PWM signal.

Output Voltage: 0.9 V ~ 1.5 V

Dynamic voltage control interface technique: PWM, active

high to VIO

System voltage used for lowering output voltage below

1.25 V: VTT = VIO = 2.5 V

Maximum output current: 700 mA

E VIN

~5V TO 8V

2.2␮F

L MLCC

ADP3088

IN

SW

IN

DRV

GND GND

CHF

O 10pF

CC

COMP FB

470pF

RC

20k⍀

10␮H@1A

1N5817

3؋10␮F

MLCC

VOUT

0.9V TO 1.5V

@700 mA

CFF

2.2nF

RA

10.0k⍀

RTT

287k⍀

VTT 2.5V

PWM 0V TO 2.5V

RPWM

41.2k⍀

OBSFigure 5. Blackfin DSP Application

–14–

REV. C

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