Preliminary Technical Data
AD5744
Parameter
DIGITAL INPUTS3
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
DIGITAL OUTPUTS (D0, D1, SDO)3
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
High Impedance Leakage
Current
High Impedance Output
Capacitance
POWER REQUIREMENTS
AVDD/AVSS
DVCC
Power Supply Sensitivity3
∆VOUT/∆ΑVDD
AIDD
AISS
DICC
Power Dissipation
B Grade2
2
0.8
±1
10
0.4
DVCC − 1
0.4
DVCC − 0.5
±1
5
11.4/16.5
2.7/5.25
−85
3.5
2.75
1.2
275
C Grade2
2
0.8
±1
10
0.4
DVCC − 1
0.4
DVCC − 0.5
±1
5
11.4/16.5
2.7/5.25
−85
3.5
2.75
1.2
275
Unit
V min
V max
μA max
pF max
V max
V min
V max
V min
μA max
pF typ
V min/V max
V min/V max
dB typ
mA/channel max
mA/channel max
mA max
mW typ
Test Conditions/Comments
DVCC = 2.7 V to 5.25 V, JEDEC
compliant
Per pin
Per pin
DVCC = 5 V ± 5%, sinking 200 μA
DVCC = 5 V ± 5%, sourcing 200 μA
DVCC = 2.7 V to 3.6 V,
sinking 200 μA
DVCC = 2.7 V to 3.6 V,
sourcing 200 μA
SDO only
SDO only
Outputs unloaded
Outputs unloaded
VIH = DVCC, VIL = DGND, 750 μA typ
±12 V operation output unloaded
2 Temperature range: -40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.
3 Guaranteed by design and characterization; not production tested.
4 Output amplifier headroom requirement is 1.4 V minimum.
Rev. PrE | Page 5 of 32