PEB2047-N データシートの表示（PDF） - Infineon Technologies

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PEB2047-N

Memory Time Switch Large

Infineon Technologies 

PEB 2047

PEB 2047-16

4.3 Status Register (STAR)

Access in the multiplexed µP-interface mode:

Access in a demultiplexed µP-interface mode:

Reset value:

01H

Read, address: 2H

Read, address: 1H

Bit 7

Z

FSAD2 FSAD1 FSAD0 B

PACT

PSS

Bit 0

STOK

Z

FSAD (2:0)

B

PACT

PSS

STOK

Note:

Incomplete instruction; a three byte indirect instruction is not completed (Z = 1).

Frame Synchronization signal Address 2 to 0: see CMDR.

Busy; an indirect access is active (memories or indirect registers); the three byte

indirect access register is not accessible.

Procedure Active; one of the procedures started by the µP (selftest, CM reset or

frame evaluation) is active.

PCM Synchronization Status; the PCM interface is synchronized (logical 1) or

not synchronized (logical 0).

Selftest O.K.; after a selftest procedure this bit is set to 1, if no faults are detected.

This bit is only valid, if no power failure or inappropriate clocking occurred during

the test (see ISTA:IR); this bit is set to 1 by a start selftest command or by

hardware reset.

Semiconductor Group

24

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