PEB2047-N データシートの表示（PDF） - Infineon Technologies

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PEB2047-N

Memory Time Switch Large

Infineon Technologies 

PEB 2047

PEB 2047-16

For a system operating with 8192-kHz device clock and 8192-Mbit/s/8192 Mbit/s input/output data

rate the following frame delay table can be deduced from the timing diagram:

Table 1

Input Time-Slot

Switched to Output Time-Slot

Switched

to

OUT1, 2, 3

0– 1

2– 3

4– 5

.

.

.

118 – 119

120 – 121

122 – 123

124 – 125

126 – 127

6 – 127

8 – 127

10 – 127

.

.

.

124 – 127

126 – 127

–

–

–

0– 5

0– 7

0– 9

.

.

.

0 – 123

0 – 125

0 – 127

2 – 127

4 – 127

–

–

–

.

.

.

–

–

–

0– 1

0– 3

Switched

to

OUT0

0– 1

2– 3

4– 5

.

.

.

118 – 119

120 – 121

122 – 123

124 – 125

126 – 127

7 – 127

9 – 127

11 – 127

.

.

.

125 – 127

127

–

–

–

0– 6

0– 8

0 – 10

.

.

.

0 – 124

0 – 126

1 – 127

3 – 127

5 – 127

–

–

–

.

.

.

–

–

0

0– 2

0– 4

Delay/number of

frames

minimal delay 0

constant delay 1

1

2

1

3

From this table it can be seen, that it is not possible to achieve the constant delay of one frame for

all switching paths. Those input time-slots, which are written to the data memory later than they

should have been read (for example in the above configuration TS124 – TS127 switched to TS0 or

TS1, OUT1, 2, 3), will be delayed by three frames!

Semiconductor Group

17

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