Nexperia
13. Package outline
74LVC1G38
2-input NAND gate; open drain
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
627
'
\
=
H
ES
H
Z 0
(
$
;
F
+(
Y 0 $
$
$
$
$
ș
/S
/
GHWDLO;
PP
VFDOH
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
81,7
$
PD[
$
$
$
ES
F ' ( H
H
PP
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
287/,1(
9(56,21
,(&
5()(5(1&(6
-('(&
-(,7$
627
02
6&$
+( / /S Y
Z
\
=
ș
(8523($1
352-(&7,21
,668('$7(
Fig 10. Package outline SOT353-1 (TSSOP5)
74LVC1G38
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 7 December 2016
© Nexperia B.V. 2017. All rights reserved
9 of 19