HI5766KCBZ データシートの表示（PDF） - Renesas Electronics

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HI5766KCBZ

10-Bit, 60MSPS A/D Converter

Renesas Electronics 

HI5766

Timing Definitions

Refer to Figure 1 and Figure 2 for these definitions.

Aperture Delay (tAP)

Aperture delay is the time delay between the external

sample command (the falling edge of the clock) and the time

at which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

Aperture Jitter (tAJ)

Aperture jitter is the RMS variation in the aperture delay due

to variation of internal clock path delays.

Data Hold Time (tH)

Data hold time is the time to where the previous data (N - 1)

is no longer valid.

Data Output Delay Time (tOD)

Data output delay time is the time to where the new data (N)

is valid.

Data Latency (tLAT)

After the analog sample is taken, the digital data representing

an analog input sample is output to the digital data bus on

the 7th cycle of the clock after the analog sample is taken.

This is due to the pipeline nature of the converter where the

analog sample has to ripple through the internal subconverter

stages. This delay is specified as the data latency. After the

data latency time, the digital data representing each

succeeding analog sample is output during the following

clock cycle. The digital data lags the analog input sample by 7

sample clock cycles.

Power-Up Initialization

This time is defined as the maximum number of clock cycles

that are required to initialize the converter at power-up. The

requirement arises from the need to initialize the dynamic

circuits within the converter.

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FN4130 Rev 6.00

March 30, 2005

Page 16 of 16

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