CS51313 データシートの表示（PDF） - ON Semiconductor

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CS51313

Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators

ON Semiconductor 

CS51313

Error Amplifier

An inherent benefit of the V2 control topology is that there

is no large bandwidth requirement on the error amplifier

design. The reaction time to an output load step has no

relation to the crossover frequency, since transient response

is handled by the ramp signal loop. The main purpose of this

“slow” feedback loop is to provide DC accuracy. Noise

immunity is significantly improved, since the error

amplifier bandwidth can be rolled off at a low frequency.

Enhanced noise immunity improves remote sensing of the

output voltage, since the noise associated with long

feedback traces can be effectively filtered. The COMP pin

is the output of the error amplifier and a capacitor to GND

compensates the error amplifier loop. Additionally, through

the built−in offset on the PWM Comparator non−inverting

input, the COMP pin provides the hiccup timing for the

Overcurrent Protection, the Soft Start function that

minimizes inrush currents during regulator power−up and

switcher output enable.

Reference Voltage

The CS51313 has a precision reference trimmed to 1.5%

over temperature, which is externally available for use by

other power supplies on the motherboard. For instance, the

VREF pin can be used to configure an LDO controller that

drives either a MOSFET or a bipolar transistor. The

compensation criteria on this LDO controller is set by the

dynamic performance requirement on the overall power

supply. The following circuit demonstrates the typical

connections required to implement an LDO controller using

the CS51313 VREF pin.

+3.3 V

+1.5 V

External N−FET

CIN

+12 V

R1 21.9 k

CO

0.5%

−

+

R2 100 k

0.5%

VREF

Figure 9. VREF Used in an N−FET LDO Regulator

The applications diagram shows a pair of linear regulators

for VGTL and VCLOCK. The 1.23 V VREF of the CS51313 is

used as the reference for both regulators. The feedback

resistors determine the output voltage for each regulator. In

this case, it will be 1.5 V @ 3.0 A for VGTL and 2.5 V @

1.0 A for VCLOCK. In Figure 9 the ratio of resistor R1 to

resistor R2 is (VOUT/VREF) − 1, where VOUT = 1.5 V and

VREF = 1.23 V. The same formula can be used to determine

the ratio of the feedback resistors needed to implement a

2.5 V linear regulator (VOUT = 2.5 V). To negate the bias

current of the operational amplifier, a resistor with a value

equal to the parallel combination of the feedback resistors

(R1//R2) is connected in series with the non−inverting input

of this operational amplifier. R2 sets the minimum output

current, (IMIN = VREF/R2).

The pass transistor must be able to dissipate the power

adequately while keeping the junction temperature below

the maximum specified by the manufacturer. For example,

with VGTL output of 1.5 V, input voltage of 3.3 V, and output

DC current of 3.0 A, the pass transistor dissipates (3.3 V −

1.5 V) × 3.0 A = 5.4 W.

Sufficient output capacitance must be added to ensure that

the output voltage remains within specification during

transient loading. For example, the GTL bus load can ramp

from 0 to 2.7 A at a rate of 8 A/μs. The designer needs to

verify that the circuit will meet these requirements using the

transistor and operational amplifier chosen.

Startup

The CS51313 provides a controlled startup of regulator

output voltage and features Programmable Soft Start

implemented through the Error Amp and external

Compensation Capacitor. This feature, combined with

overcurrent protection, prevents stress to the regulator

power components and overshoot of the output voltage

during startup.

As power is applied to the regulator, the CS51313

Undervoltage Lockout circuit (UVL) monitors the IC’s

supply voltage (VCC) which is typically connected to the

+12 V output of the AC−DC power supply. The UVL circuit

prevents the NFET gates from being activated until VCC

exceeds the 8.4 V (typ) threshold. Hysteresis of 300 mV

(typ) is provided for noise immunity. The Error Amp

Capacitor connected to the COMP pin is charged by a 30 μA

current source. This capacitor must be charged to 1.1 V (typ)

so that it exceeds the PWM comparator’s offset before the

V2 PWM control loop permits switching to occur.

When VCC has exceeded 8.4 V and COMP has charged to

1.1 V, the upper Gate driver (GATE(H)) is activated, turning

on the upper FET. This causes current to flow through the

output inductor and into the output capacitors and load

according to the following equation:

I + (VIN * VOUT)

T

L

GATE(H) and the upper NFET remain on and inductor

current ramps up until the initial pulse is terminated by either

the PWM control loop or the overcurrent protection. This

initial surge of in−rush current minimizes startup time, but

avoids overstressing of the regulator’s power components.

The PWM comparator will terminate the initial pulse if

the regulator output exceeds the voltage on the COMP pin

plus the 1.1 V PWM comparator offset before the voltage

drop across the current sense resistor exceeds the current

limit threshold voltage. In this case, the PWM control loop

has achieved regulation and the initial pulse is then followed

by a constant off time as programmed by the COFF capacitor.

The COMP capacitor will continue to slowly charge and the

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