LCK4801 データシートの表示（PDF） - Agere -> LSI Corporation

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LCK4801

Low-Voltage HSTL Differential Clock

Agere -> LSI Corporation 

LCK4801

Low-Voltage HSTL Differential Clock

Preliminary Data Sheet

July 2001

Applications

Power Supply Filtering

The LCK4801 is a mixed analog/digital product. Because of this, it exhibits some sensitivities that would not

necessarily be seen on a fully digital product. Analog circuitry is susceptible to random noise, the worst case being

when this noise is seen on the power supply pins. The LCK4801 provides separate power supplies for the output

buffers (VDDHSTL) and the phase-locked loop (VDDA) of the device in order to isolate the high digital output

switching noise from the internal analog PLL. In a controlled evaluation board environment, this level of isolation is

adequate. However, in a digital system, a second level of isolation is suggested.

The easiest way to accomplish this is to add a power supply filter on the VDDA pin of the LCK4801. Figure 5 on

page 9 shows the typical power supply scheme. The filter should be designed in the 10 kHz—1 MHz range, since

this is the most likely frequency range to cause spectral content noise.

Note the dc voltage drop between VDDD and VDDA on the power supply filter. Very little dc voltage drop can be

tolerated when a 3.3 V VDDD supply is used. The power supply filter in Figure 5 must be 5 Ω—10 Ω in order to

meet the drop criteria. The RC filter in Figure 5 will provide a broadband filter with approximately 100:1 attenuation

above 20 kHz.

The impedance of an individual capacitor begins to appear inductive and increases with frequency as the noise

frequency crosses the series resonant point of the capacitor. The parallel capacitor combination ensures that for

frequencies much greater than the bandwidth of the PLL there is always a low-impedance path.

8

Agere Systems Inc.

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